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The ROHD Hardware Component Library (ROHD-HCL): a collection of reusable, configurable ROHD components.

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0.3.1 #

  • Fixed the published package's workspace metadata so consumers do not need the separate Confapp application.

0.3.0 #

Behavioral models #

  • Uncertain memory writes now report through the active ROHD-VF test logger, falling back to a printed warning when no verification test is active.
  • Added RTL configurator entries for cache compositions, cache scheduling and transaction transport, reusable replacement policies, and inferred SRAM. Experimental cache entries are labeled; the SRAM appears as a schematic cell inside a structural wrapper.
  • Marked cache-specific controllers, ports, contracts, adapters, schedulers, replacement factories, and behavioral cache/backing-store APIs @experimental; they may change without a version bump. General associative, replacement-policy, and memory-storage APIs are not marked experimental by this change.
  • CSR block bases, offsets, extents, logical chunk increments, and software state now support arbitrary-width addresses in RTL, Dart, and SystemC. RTL and software consistently reject overlapping or out-of-range chunks, and Verilog now matches four-state unknown-address read/write behavior.
  • Preserved arbitrary-width sparse addresses in memory-file import/export and snapshots; added BigInt raw access and removed width limits from CSR frontdoor and clock-stepped associative SystemC decoding.
  • Added a port-compatible parallel associative behavioral model with shared storage, state snapshots, and combinational four-state Dart and SystemC behavior. It can supply cache tags through the common associative factory. Unknown synchronous reset now consistently poisons parallel associative RTL state in both ROHD simulation and Verilog.
  • Added directed wide-tag and wide-index associative regressions for concurrent updates, duplicate selection, masked matching, invalid aliases and snapshots, including RTL, Verilog, Dart and SystemC where applicable.
  • Parallel associative Dart and four-state SystemC models now poison state on invalid clock transitions as ROHD RTL does. Invalid-clock Verilog edge semantics remain different and are documented.
  • Corrected four-state associative key comparisons to retain definite mismatches despite unknown bits, consistently across RTL simulation, Verilog, and Dart and SystemC behavioral models.
  • Added a standalone behavioral fixed-priority cache scheduler for Dart and SystemC, with three-way comparisons against generated Verilog including four-state inputs.
  • Behavioral round-robin and tree pseudo-LRU replacement policies now preserve RTL four-state behavior and export standalone SystemC models with snapshots. Their synchronous reset and partial-index comparisons also agree between ROHD simulation and generated Verilog when inputs contain unknown bits.
  • Added common register-file and one-cycle, single-port inferred SRAM array factories. The SRAM provides execution snapshots and standalone SystemC and can back serialized-cache data independently of flop-based tags. Serialized cache metadata can use a separate combinational-read array factory.
  • Added an explicit two-state SystemC hierarchy exporter that substitutes selected portable behavioral models while retaining structural RTL elsewhere. An SRAM-backed serialized cache is compared across Dart, Verilog, and SystemC.

Breaking changes #

  • CSR address, block-size, and logical-register-increment getters, description maps, addressOf, and software snapshot keys now use BigInt. Existing integer configuration constructors remain available; use the .wide constructors and BigInt lookup and state methods for arbitrary-width values.

  • MemoryStorageImage.entries now uses BigInt address keys, and implementations of MemoryStateAccess must provide BigInt raw access.

  • Cache and its named constructors now take CacheLookupPort<T> and CacheFillPort<T> instead of individual signals. Drive inputs and consume outputs on those ports, as with MultiPortCache. Cache lookup, fill, scheduler and transaction ports are cloneable ROHD pair interfaces.

  • Multipliers, multiply-accumulates, dot products, partial-product building blocks and ones-complement adders now accept StaticOrRuntimeParameter controls instead of raw bool or Logic values. Construct static controls with staticValue and runtime controls with runtime or fromLogic. Multiplier-generator and adder callbacks use the same typed controls.

  • CarrySelectCompoundAdder block-adder callbacks now accept subtract instead of subtractIn. PartialProduct custom genPPG callbacks and PPGFunction now use unified signedMultiplicand and signedMultiplier controls instead of separate static and runtime arguments.

  • Automatic PartialProduct definition names now include radix and distinguish static from runtime signedness. Consumers that reference these generated HDL names must update them; explicit definitionName values are unchanged.

  • Automatic OnesComplementAdder, CarrySelectCompoundAdder, and CarrySelectOnesComplementCompoundAdder definition names now distinguish static addition, static subtraction, and runtime subtraction. Explicit definitionName values are unchanged.

  • SPI main and sub gaskets now asynchronously clear receive state and capture transmit data on the first enabled SPI rising edge instead of asynchronously loading busIn on reset. Hold busIn stable through the first falling SPI edge; busOut is zero immediately after reset. This avoids dynamic asynchronous reset values. See SPI Gaskets.

  • Ready/valid interfaces no longer preserve the deprecated PairInterface.modify callback. Pass uniquify when connecting or registering an interface instead; naming is now configured at the connection rather than stored on the clone.

  • Interface registration now uses ROHD's addInterfacePorts and addPairInterfacePorts APIs throughout components, tests, and examples. Tag selection, pair roles, typed payloads, and port naming are unchanged.

  • Parity/ECC transmitters and receivers now preserve payload types. Receivers accept an optional dataSchema for typed original/corrected data; without it they retain ordinary Logic outputs. Custom error-checker subclasses should specify their payload type and return that type from calculateCorrectedData. Use explicit <Logic> when transmitting scalar constants. Encoded wire formats are unchanged.

  • ClockGate.controlled<T> preserves payload type and width, fixing delayed multi-bit signals. Use controlled<Logic> for delayed scalar constants.

  • ReadyValidFifo<T> now accepts any Logic payload.

  • CSR write/read candidate builders and bit replacement now return structured Csr values.

  • Floating-point swap/sort classes now take independent <FpType, MetaType> arguments and expose metadata as MetaType?. Explicit one-argument annotations must add the metadata type; inferred calls remain supported. Use Logic for scalar constant metadata. Metadata layouts, enum mappings, and codecs must match.

  • Prefix topologies now preserve their payload type as ParallelPrefix<T>, Ripple<T>, Sklansky<T>, KoggeStone<T>, and BrentKung<T>. Use <Logic> for scalar constant inputs. Custom ParallelPrefixAdder.ppGen generators must use ParallelPrefixGenerator<GeneratePropagate> and preserve named generate/propagate fields instead of packed two-bit pairs. Built-in constructor tear-offs remain supported.

  • ShiftRegister<T> and AsyncFifo<T> preserve payload types. Use explicit <Logic> for scalar constant inputs.

  • Extrema<T> preserves payload types and defaults to the payload's comparison rather than flattening domain-specific signals into unsigned bits; pass .packed inputs for packed-bit ordering. Use explicit <Logic> for scalar constant inputs. Ordinary scalar width extension and earliest-index tie breaking are unchanged.

  • Sorting now preserves payload types. Use BitonicSort<Logic> when scalar constant inputs should become mutable ports/state. Typed sorting uses the payload's numeric comparisons by default; pass .packed inputs for the prior unsigned packed ordering.

  • Reduction now preserves payload types. Use ReductionTree<Logic, Logic> and ReductionTreeGenerator<Logic, Logic> when scalar constant inputs should become mutable ports/state. Structured reduction callbacks now own field/format alignment instead of receiving flattened, bit-extended operands.

  • Toggle gating now preserves payload types. Use ToggleGate<Logic> when scalar constant inputs should become mutable ports/state.

  • condFlop now preserves its input's static type and runtime payload schema. When registering a scalar Const or LogicNet, request condFlop<Logic>(...) explicitly to construct a driveable result. Null-clock calls still return their original input.

  • Serializer<T, V> and Deserializer<T, V> now support typed array leaves while preserving outer-dimension transfer timing. Both data outputs are TypedLogicArray<T, V>; serialization of a one-dimensional input yields a rank-zero array, with the typed leaf accessible via .scalar. The deserializer constructor requires a leaf valueCodec; use LogicValueCodec.logicValue for existing plain-logic callers. See Serialization.

  • The minimum supported Dart SDK is now 3.6.0. Applications using Dart 3.0 through 3.5 must upgrade their SDK before resolving ROHD-HCL.

  • Removed splitSelectAdderAlgorithm4Bit, deprecated in v0.2.1; use splitSelectAdderAlgorithmNBit(4).

  • Removed the interface clone and divider match constructors deprecated in v0.2.1; use instance clone().

  • Removed the partial-product sign-extension wrappers deprecated in v0.2.1; use the corresponding PartialProductSignExtension strategy.

  • Removed Count.index, deprecated in v0.2.1; use count.

  • Removed the parity getters deprecated in v0.2.1; use code/error/originalData.

  • FixedPointValue comparison operators now return bool, completing the transition announced in v0.2.1.

  • Corrected AXI5 signal widths to match the configured protocol widths. Generated interfaces for affected MMUSID, MMUSSID, and SUBSYSID signals may have different port widths; designs that connect to those signals must use the corrected widths (https://github.com/intel/rohd-hcl/pull/280).

  • ChoiceConfigKnob<Type> now requires a stable label for every choice, including on the Dart VM, because Type.toString() is not stable in minified builds. The labels are used as both display text and serialized JSON values. Existing custom configurators must migrate to the choiceLabels construction pattern:

    ChoiceConfigKnob<Type>(
  [BinaryToOneHot, OneHotToBinary],
  value: OneHotToBinary,
  choiceLabels: const {
    BinaryToOneHot: 'BinaryToOneHot',
    OneHotToBinary: 'OneHotToBinary',
  },
);

    Labels matching the previous unminified type names, as used by the built-in configurators, preserve compatibility with existing saved values.

  • FloatingPointSqrtSimple now rejects explicit-J-bit inputs. Use an implicit-J-bit format or normalize the input before connecting it to the square-root component.

  • Explicit-J-bit NaN construction now requires at least one payload bit in addition to the J bit. Formats with a one-bit explicit mantissa are rejected because they cannot encode a quiet-NaN payload.

  • Automatic definition names for MultiplyAccumulate, CompressionTreeMultiplyAccumulate, and GenericMultiplyAccumulate now include the effective outputWidth. Consumers that reference generated HDL definition names must update those names; explicitly supplied definitionName values are unchanged.

  • Automatic FixedToFloat, FloatingPointAdderSinglePath, FloatingPointConverter, FloatingPointSqrt, and FloatingPointSqrtSimple definition names now include roundingMode so modules with different rounding logic cannot share an HDL definition. Consumers that reference generated HDL definition names must update those names; explicitly supplied definitionName values are unchanged.

  • Automatic DotProduct, CompressionTreeDotProduct, and GeneralDotProduct definition names now include lane count, operand widths, radix, implementation identity, and signedness. Consumers that reference generated HDL definition names must update those names; explicitly supplied definitionName values are unchanged.

  • Automatic Count definition names now include the tree radix.

  • Automatic Extrema definition names now include the tree radix and input widths. Consumers referencing the generated Count or Extrema HDL definition names must update them; explicitly supplied definitionName values are unchanged.

  • Removed PartialProductMatrix.array, which exposed the internal partial-product generator. Apply custom transformations through the beforeGenerateOutputs callback to generateOutputs.

  • Made implementation-only hardware signals and connected interface clones non-public. Consumers must use documented module outputs and caller-owned interfaces instead of accessing child internals directly.

  • Reorganized lib/src into a category/subcategory directory taxonomy. The public package:rohd_hcl/rohd_hcl.dart API is unchanged, but code that imports private package:rohd_hcl/src/... paths directly must update those paths or import the package barrel instead.

  • Generated Fifo definitions retain their existing automatic definition names and latency, but now include the protocol-neutral canEnqueue, outputValid, and slotReleased output ports. External positional SystemVerilog instantiations of generated FIFO definitions must account for the additional outputs; named-port instantiations may leave them unconnected.

  • Counter.overflowed and Counter.underflowed (including GatedCounter) are now nullable. The corresponding generated status port exists only when trackOverflow or trackUnderflow, respectively, is true; callers that disable tracking must handle a null getter instead of a tied-low signal.

Deprecated APIs #

  • Deprecated ReadyValidFifo while retaining its existing behavior. Use ReadyValidQueue with registered policy and ring storage; unlike the legacy default, the queue permits a full dequeue and enqueue on the same edge.
  • Deprecated Cam and TagInterface while retaining their existing behavior. Use ParallelAssociativeMemory and the role-specific associative ports, including typed ports for structured keys. Lookup enable and four-state comparison semantics differ; see Memory.
  • Restored the legacy src/gaskets/gaskets.dart barrel as a deprecated compatibility import. Import package:rohd_hcl/rohd_hcl.dart instead.
  • Deprecated the unsigned-default FixedPointValue constructor and FixedPointValue.populator while preserving their existing behavior. Use FixedPointValue.withSignedness and FixedPointValue.populatorWithSignedness, which default to signed: true to match FixedPoint (https://github.com/intel/rohd-hcl/issues/249).
  • Deprecated FixedPoint.operator * while preserving its previous unsigned result width and behavior. Use FixedPoint.multiply for a correctly signed, full-width product.
  • Deprecated the static_or_runtime_parameter.dart import path. Import static_or_runtime_control.dart instead.
  • Deprecated the subtractIn constructor parameter and protected member on OnesComplementAdder and CarrySelectOnesComplementCompoundAdder. Use subtract and subtractParameter, respectively.
  • Kept the deprecated FixedPointValue.eq/neq compatibility methods. Use ==/!= instead.
  • Kept the deprecated normal/subNormal arguments to FloatingPointValuePopulator.random. Use genNormal/genSubNormal instead.
  • Kept the deprecated loadMemHex compatibility method. Use loadMemString instead.

New features and enhanced components #

  • Added simulation-only round-robin and tree pseudo-LRU replacement policies using the RTL replacement ports, including deferred commits and snapshots. Serialized-cache tests compare their timing with RTL replacement and data arrays at fixed read latencies of one through three cycles.

  • Added MemoryModel.registerFile for finite RegisterFile-matching behavior, with synchronous reset, combinational reads, matching masked-write priority, static per-entry reset values, and behavioral SystemC export.

  • Added four-state SystemC export and execution snapshots for plain-logic MemoryModel instances using built-in sparse storage. Generated RAM, CSR, and associative models share a sparse SystemC storage implementation; unsupported RAM storage, typed payloads, and two-state boundaries are rejected.

  • Added direct-mapped, set-associative, and fully associative cache composition with blocking eviction, round-robin or tree pseudo-LRU replacement, typed payloads, pluggable replacement factories, and selectable register-file or behavioral data storage. Non-evicting fills can run alongside lookups with old-data or forwarding behavior. See Associative Memory.

  • Added MultiPortCache with concurrent lookups, one accepted fill per set by default, optional distinct-way same-set fills, buffered evictions with parallel or serialized handshakes, and selectable old-data or forwarding behavior. Latency-bearing SRAM is not yet supported.

  • Added a capability-checked typed MemoryArrayFunctor for custom cache data arrays with independent and combined concurrency limits, plus persistent replacement reservations and deferred policy commits by reserved entry. The current cache presets remain zero latency.

  • MemoryModel supports full snapshots and restore of storage, read outputs, and in-flight delayed reads through direct methods and stateTransactions.

  • CsrSoftwareModel supports execution snapshots of register state and sampled event bookkeeping at simulator tick boundaries; external signals and events remain the caller's responsibility.

  • Added a clock-stepped associative software model with four-state exact and masked matching, in-flight snapshots, and a capability-limited four-state SystemC export.

  • Behavioral CSR, associative memory, and cache state now reuse the sparse storage engine used by the default MemoryModel, while preserving each family's timing and state APIs.

  • Associative-memory functors can optionally bind multiple indexed side reads without changing existing AssociativeMemoryBuilder callbacks.

  • Added protocol-neutral transactional cache and resource-scheduler contracts, including typed request, response and eviction channels, along with a fixed-priority resource scheduler, globally serialized fixed-latency SerializedCache, and bounded ready/valid CacheTransactionAdapter. Protocol-specific miss handling and nonblocking SRAM cores remain separate work.

  • Added simulation-only BehavioralCache with configurable concurrency, ordered same-set transactions, pluggable replacement, and persistent behavioral backing storage. Explicit extension operations provide read-through and write-allocate behavior without changing built-in cache operation semantics. Backing storage supports raw state images, and the cache supports full-state snapshot and restore including in-flight transactions with snapshot-capable replacement policies.

Flow control and clocking

  • Added ReadyValidInterface and ReadyValidFifo in preparation for cache componentry (https://github.com/intel/rohd-hcl/pull/281).
  • Finalized the ready/valid interface foundation with value-based ReadyValidContract metadata, typed payload port registration, accepted/stalled predicates, composability checks, clone-preserved contracts, and independent, ready-first, valid-first, and irrevocable interface variants. Typed registration preserves provider sidebands and nested pair subinterfaces, supports validated packed bridges between plain and structured payload ports, and applies uniquify naming consistently to payload, valid, ready, and recursive interface ports.
  • Added ReadyValidQueue with registered or fall-through visibility, register or ring storage, occupancy thresholds, and synchronous flush, plus a configurator.
  • Added the protocol-neutral HardwareCoreFunctor construction seam and a typed FifoCoreFunctor implementation over Fifo, including explicit full-replacement and empty-bypass capability requirements. FIFO core definition identities include a deterministic recursive payload-shape signature so equal-width but structurally different payloads cannot collide. Concrete ready/valid, credit, routing, and scheduling attachments remain later component work.
  • Added AsyncFifo for safely transferring data between clock domains (https://github.com/intel/rohd-hcl/issues/168, https://github.com/intel/rohd-hcl/pull/279). Its ports and storage preserve structured, enum, and typed-array payloads without changing delay or CDC behavior (https://github.com/intel/rohd-hcl/issues/257).
  • Synchronous FIFO storage preserves typed payloads; ready/valid adapters share recursive typed-array shape validation and FIFO definition identities.
  • Exposed the module name argument on round-robin and related arbiters (https://github.com/intel/rohd-hcl/pull/255). RotateRoundRobinArbiter also handles zero or one request (https://github.com/intel/rohd-hcl/pull/305).
  • ToggleGate preserves typed data and control through its storage and selection.

Memory

Interfaces

  • Refactored AMBA support to add AXI4-Lite, AXI4-Stream, ACE, and ACE-Lite protocol variants while preserving the existing AXI APIs (https://github.com/intel/rohd-hcl/pull/251).
  • Added an abstract ApbCompleter and an ApbCsrCompleter implementation for connecting APB transactions to CSR blocks (https://github.com/intel/rohd-hcl/pull/270).
  • AXI4/AXI5 request and response channels and LTI read responses provide opt-in typed enum views. Raw ports remain unchanged; invalid-value normalization in functional simulation is not guaranteed in generated HDL. See AXI.

Dataflow and shared utilities

  • Extrema selects typed payload/index candidates using typed muxes and supports a custom strict isLessThan comparator for record keys. Its radix parameter combines candidates with a balanced ReductionTreeGenerator tree instead of a linear comparison chain.
  • Bitonic sort preserves typed data and control through its stages and supports a custom strict isLessThan comparator while transporting complete records and typed arrays.
  • Both reduction implementations preserve typed data and control.
  • Added optional early termination to Serializer and Deserializer for dynamically sized inputs (https://github.com/intel/rohd-hcl/issues/277, https://github.com/intel/rohd-hcl/pull/278).
  • Shared swaps and optional flops preserve floating-point subtypes, fixed-point formats, enum mappings, and typed-array schemas.
  • Floating-point swap/sort metadata ports retain structured payloads; arithmetic field operations and pipeline timing are unchanged.

Bit operations

  • Added Pad, which widens to a minimum width with zeros or ones at the LSB or MSB end, SetBits, which sets a count of LSBs or MSBs to zeros or ones, and WithSet.
  • Added OneHotMux, PriorityMux, and BitwiseMux, which supports N inputs and per-bit one-hot selects. The one-hot mux validates its cases and selector width and addresses https://github.com/intel/rohd-hcl/issues/95.
  • Added BitwisePopcount with XorPopcount and XnorPopcount.
  • Added a radix parameter to Count so its population count is combined with a balanced ReductionTreeGenerator tree instead of a linear accumulation chain.
  • Rotation now also offers fixed left and right implementations.

Arithmetic building blocks

  • Added UnsignedAddWithOverflow, UnsignedMulWithOverflow, CeilDivide, Log2Ceil, and AbsoluteValue, which widens by one bit so the minimum value is representable.
  • Added CircularPointer for wrapping slot indices of any slot count.
  • Preserved structures, enum mappings, and typed-array schemas through prefix ports, callback results, recursive networks, and internal aliases. Added explicit structured-layout validation while retaining scalar widths and operand order. Prefix adders use typed generate/propagate records internally; external arithmetic ports and carry behavior are unchanged.

Floating-point and fixed-point payloads

  • FloatToFixed<T> accepts an optional signed outFixed schema, preserves its concrete subtype internally and on output, and validates explicit width compatibility. Scalar defaults remain unchanged. Float8ToFixed preserves structured input schemas while retaining its intentionally mode-dependent scalar output.
  • Fixed-point square root retains its concrete output subtype; floating-point square-root selection preserves its fixed-point intermediate schema.
  • Floating-point adders and the simple multiplier carry NaN payloads through typed optional pipeline stages and use whole-payload typed muxes for final propagated/default NaN selection.

IEEE rounding compatibility

  • Added all FloatingPointRoundingModes to floating-point value and logic operations, including adders, multipliers, converters, square root, FixedToFloat, and FloatToFixed (https://github.com/intel/rohd-hcl/issues/191).
  • Added roundingMode to FixedToFloat and FloatToFixed, retaining their previous defaults of roundNearestEven and truncate, respectively.
  • Unified fixed- and floating-point value rounding APIs (https://github.com/intel/rohd-hcl/issues/173).

Conversions

Arithmetic signal operations

Integer arithmetic components

  • Added an optional carryIn to SignMagnitudeAdder.
  • Added configurable outputWidth to MultiplyAccumulate, CompressionTreeMultiplyAccumulate, and MultiplyOnly.
  • Added GenericMultiplyAccumulate, which composes configurable multiplier and adder generators.
  • Added independent multiplicand and multiplier widths to NativeMultiplier and GeneralDotProduct; CompressionTreeDotProduct retains its equal-width fused-partial-product contract.

Accumulation

Parameterized Configuration

  • Added generic StaticOrRuntimeControl<T> support for statically configured values or multi-bit runtime Logic inputs while preserving StaticOrRuntimeParameter as the boolean specialization.
  • Added child-module rebinding and static-pruned or runtime-mux selection to static-or-runtime controls. Low-level multiplier signedness and compound-adder block callbacks now use the same control model as top-level components.

Source Organization

  • Grouped existing components into top-level categories: arithmetic, bit_operations, clocking, dataflow, encodings, error_control, flow_control, interfaces, memory, and models. Each category has functional subcategories, such as arithmetic/addition, clocking/cdc, flow_control/arbitration, flow_control/ready_valid, and memory/csr.
  • Added category barrels and subcategory barrels where useful, so related components can be imported selectively. lib/rohd_hcl.dart now exports the category barrels.
  • Moved tests under their matching category directories and subdivided larger families by source subcategory.
  • Renamed the misspelled internal mulitiplier_components.dart barrel to multiplication/multiplier_components.dart.

Configurator Taxonomy

  • Added ComponentCategory and Configurator.category/Configurator.subcategory so configurators can describe where a component belongs in the library taxonomy. Custom configurators default to ComponentCategory.other and 'uncategorized'.
  • Tagged all built-in configurators with their category and subcategory.

Configuration application and schematics #

  • Migrated the configuration application and generated API-documentation schematics from the legacy D3 flow to rohd_schematic_viewer. The new flow renders native ROHD netlists, retains Yosys-based synthesized schematics, and redirects existing component schematic URLs to the new viewer.
  • Added selectable ROHD schematic, ROHD source, generated SystemVerilog, and synthesized schematic views, including syntax highlighting, downloadable generated artifacts, configurable schematic expansion, and split-pane output.
  • Migrated the configuration application to material_ui, including light and dark themes, and removed its legacy Flutter Material dependencies.
  • Converted the root package and configuration application to a Pub workspace and added package-by-package hosted, Git, and local dependency-source selection for development.
  • Updated the source-view asset mapping and generated asset list for the reorganized source tree.
  • Replaced plain-text integer parameter fields in confapp with validated IntegerKnobControl steppers, supporting unit increment/decrement, hexadecimal input, optional blank values, and inline validation. The implementation is in confapp/lib/hcl/view/screen/integer_knob_control.dart, with tests mirrored under confapp/test/hcl/view/screen/.
  • Added PositiveIntConfigKnob (minimum 1), NonNegativeIntConfigKnob (minimum 0), and optional IntConfigKnob.minValue; ordinary integer knobs retain signed values. Applicable component parameters declare their lower bounds while retaining defaults and saved JSON formats. Invalid integer text and below-minimum assignments now throw rather than silently retaining old values.
  • Expanded the configuration application catalog, including configurators for absolute value, circular pointers, ceil division, mux and bitwise-popcount variants, bit manipulation, synchronizers, ready/valid FIFOs, and a two-register CSR example. The catalog excludes deprecated ReadyValidFifo and Cam in favor of their replacements; their configurators remain available programmatically. See ready/valid and memory for behavioral differences.
  • Grouped the component catalog into compact, expandable, initially collapsed category and subcategory menus using configurator metadata.
  • Bundled Roboto Mono for generated source output.
  • Added configuration controls for Count/Extrema radix and static-or-runtime summation values, Counter reset behavior, and overflow/underflow tracking.
  • Added a lock toggle to the configuration application component menu; when unpinned, the menu slides out on hover from the left edge and hides when the pointer leaves.
  • Added a lock toggle to the configuration application output toolbar; when unpinned, the toolbar slides down on hover from the top edge and hides when the pointer leaves.

Documentation #

  • Reorganized the component list in doc/README.md by taxonomy and added a source-layout table that maps categories to their barrels and subcategories.
  • Updated the new-component instructions in CONTRIBUTING.md and doc/Component.md to cover taxonomy directories, subcategory barrels, family-based test locations, configurator category tags, and confapp source assets.
  • Added guides for protocol composition and associative-memory contracts, implementation selection, and migration from legacy CAM.
  • Fixed stale source paths in component documentation.

Bug fixes #

IEEE rounding compatibility bugs

  • Corrected round-nearest-even sticky-bit handling in FloatingPointMultiplierSimple near the subnormal boundary (https://github.com/intel/rohd-hcl/issues/194).
  • Replaced FixedToFloat's custom rounding with the shared FloatingPointRounder.
  • Verified round-nearest-even behavior across mantissa widths and subnormal boundaries (https://github.com/intel/rohd-hcl/issues/190).
  • FixedToFloat overflow results now respect the selected rounding mode and use the largest finite value for formats without infinity.

Conversion fixes

  • Fixed FloatingPointConverter when narrowing the mantissa and widening the exponent of a subnormal value (https://github.com/intel/rohd-hcl/issues/241).
  • Fixed FloatToFixed conversion from explicit-j-bit formats.
  • Fixed FloatToFixed overflow detection for reduced precision, rounding carry, and the exact negative power-of-two boundary.
  • Fixed wide FloatingPointValue.toString(integer: true) conversions.

NaN and special values

  • Fixed single-path floating-point addition of infinities and NaNs when input J-bit formats differ, including infinity signs and invalid-operation status. Shared NaN propagation preserves the selected input's format and payload.
  • Corrected IEEE-754 NaN comparisons and added hasSameEncoding() (https://github.com/intel/rohd-hcl/issues/252).
  • Fixed explicit-j-bit infinity and NaN encodings and quiet/signaling NaN classification.
  • Fixed E4M3 exponent limits and prevented finite results from rounding into its reserved NaN encoding (https://github.com/intel/rohd-hcl/issues/115).
  • Fixed FloatingPointValuePopulator.random(excludeInfinity: true) for formats without infinity.
  • Fixed FloatingPointValue.isLegalValue() accepting explicit-j-bit unnormal encodings.

Subnormal handling

Fixed-point fixes

  • Added FixedPoint.multiply to produce a correctly signed, full-width product.
  • Fixed FixedPointValuePopulator.canStore() to use the rounded value and the asymmetric two's-complement range.

Integer arithmetic component fixes

  • Preserved independent runtime signedness controls for multipliers and multiply-accumulates, including unnamed controls, and allowed one named signal to control both compression-tree multiplier operands. Conflicting scalar runtime-control input names now throw instead of silently aliasing.
  • Fixed GeneralDotProduct truncating intermediate sums and sign-extending unsigned products in uneven reduction trees. Static and runtime operand signedness now control partial-sum extension.
  • Fixed GeneralDotProduct passing static signedness to child multipliers as constant-valued runtime ports, and strengthened automatic definition names with lane count, operand widths, radix, implementation identity, and signedness.
  • Fixed runtime-signed GeneralDotProduct synthesis by keeping its signed-extension control inside the inline reduction generator rather than capturing a parent signal across a reduction-module hierarchy boundary.
  • Fixed CarrySaveMultiplier ignoring enable instead of stalling every pipeline stage.

Flow Control

  • Fixed AsyncFifo incorrectly advancing its write pointer when full and its read pointer when empty.

Encodings

  • Replaced BinaryToGrayConverter and GrayToBinaryConverter's O(2^width) Case-based logic with linear XOR-based conversion.

Floating-point arithmetic

  • Floating-point overflow uses a full magnitude comparison without an always-false mantissa comparison.
  • Made FloatingPointValue.operator / exact and correctly rounded for arbitrary widths, removing its host-double dependency (https://github.com/intel/rohd-hcl/issues/113).
  • Fixed FloatingPointMultiplierSimple when the output format is narrower than its inputs (https://github.com/intel/rohd-hcl/issues/194).
  • Fixed FloatingPointValue() forwarding of the signed argument.

Tooling and compatibility #

Verification and maintenance #

  • Added common smoke coverage for the generic FloatingPointValue and all named formats (https://github.com/intel/rohd-hcl/issues/133).
  • Corrected the floating-point truncating exhaustive test's overflow oracle.
  • Extended typed storage regressions to check unpacked payloads with Icarus and to compare plain and typed FIFOs with SystemC using explicit clock edges.
  • Expanded exhaustive coverage for conversions, rounding, floating-point arithmetic, fixed-point multiplication, and multiply-accumulate widths.
  • Reduced redundant randomized/exhaustive test matrices and deferred parameterized DUT construction until test execution, retaining boundary and configuration coverage while lowering test time and peak simulator memory.
  • Re-enabled previousFloatingPointValue regressions after the upstream ROHD fix (https://github.com/intel/rohd/pull/565).
  • Resolved stale arithmetic TODOs where exhaustive testing confirmed the existing implementation.
  • Added copyright and author headers to all source, test, and example Dart files that lacked them.

Known issues #

  • Berkeley TestFloat integration remains unimplemented (https://github.com/intel/rohd-hcl/issues/135).
  • MultiCycleDivider improvements remain in a stale pull request (https://github.com/intel/rohd-hcl/issues/139).
  • A 4:2 ColumnCompressor remains in a stale pull request (https://github.com/intel/rohd-hcl/issues/120).
  • Static range analysis cannot prune overflow/underflow logic when bounds or initial-value ranges are dynamic; those checks are conservatively retained.
  • CompressionTreeMultiplyAccumulate can discard precision when c exceeds its natural accumulation width; GenericMultiplyAccumulate does not.
  • Potential optimizations remain in compact sign extension.
  • Potential optimizations remain in FixedToFloat exponent prediction.
  • Potential optimizations remain in the dual-path floating-point adder N-path.

0.2.1 #

0.2.0 #

0.1.0 #

  • The first formally versioned release of ROHD-HCL.

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The ROHD Hardware Component Library (ROHD-HCL): a collection of reusable, configurable ROHD components.

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collection, meta, rohd, rohd_vf

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