rohd_bridge 0.2.4

A ROHD-based framework for connectivity and assembly of hardware designs.

0.2.4

• Added allowIntermediateSignalNameUniquification to connectPorts and port-reference connections, defaulting to true. Setting it to false reserves the resolved intermediate name. Stricter requests can create separate aliases for new fan-out receivers and bidirectional nets while preserving existing connections; unsupported custom clones and rewiring already-connected non-net receivers are rejected (https://github.com/intel/rohd-bridge/pull/68).
• Added intermediate signal naming for arrays, structures, and array selections, preserving aggregate shape and existing hierarchy port representations. Reuse is tracked for Bridge-created intermediates rather than discovered from manually connected signals (https://github.com/intel/rohd-bridge/pull/68).
• Changed connectPorts to default intermediate signal names to the explicitly supplied receiver path name, then driver path name, when intermediateSignalName is omitted. Generated RTL net names may change for explicitly named paths (https://github.com/intel/rohd-bridge/pull/67).
• Added non-connecting validate methods for references and port maps so deferred mappings can be checked before use (https://github.com/intel/rohd-bridge/pull/66).
• Improved ConnectionExtractor performance for large designs (https://github.com/intel/rohd-bridge/pull/62).
• Added sameModuleConnectionType to connectInterfaces and InterfaceReference.connectTo to select loopback or passthrough connections between interfaces on the same module (https://github.com/intel/rohd-bridge/pull/59).
• Added typed port lookup and conversion through TypedPortReference, typedPort, tryTypedPort, asTyped, and tryAsTyped (https://github.com/intel/rohd-bridge/pull/58).
• Added tryInterface, typedInterface, and tryTypedInterface for nullable and type-preserving interface lookup (https://github.com/intel/rohd-bridge/pull/58).
• Added type-preserving interface hierarchy APIs: pullUpTypedInterface, punchUpToTyped, and punchDownToTyped. These APIs intentionally omit port exclusions because a partial interface cannot retain its concrete type (https://github.com/intel/rohd-bridge/pull/58).
• Breaking: Raised the minimum supported Dart SDK from 3.0 to 3.3 for extension type support (https://github.com/intel/rohd-bridge/pull/58).
• Fixed port references and ConnectionExtractor support for typed structure ports, including nested structures, packed field slices, tie-offs, zero-width leaves, and inOut nets (https://github.com/intel/rohd-bridge/pull/61).
• Added support for custom synthesizer configurations in buildAndGenerateRTL and raised the minimum ROHD dependency from 0.6.9 to 0.6.10 (https://github.com/intel/rohd-bridge/pull/55).
• Fixed mapped interface port operations to resolve deferred PortMaps before use (https://github.com/intel/rohd-bridge/pull/50).
• Added support for same-module connections involving mapped interface ports (https://github.com/intel/rohd-bridge/pull/53).
• Added validation that rejects exact duplicate PortMap registrations (https://github.com/intel/rohd-bridge/pull/54).
• Added tryPort for nullable port lookup (https://github.com/intel/rohd-bridge/pull/43).
• Fixed output file naming in buildAndGenerateRTL for uniquified modules (https://github.com/intel/rohd-bridge/pull/46).
• Fixed hierarchical port reuse for repeated connectPorts fan-out, including explicitly named paths, partial routes, slices, and inOut ports (https://github.com/intel/rohd-bridge/pull/64).
• Simplified tie-off signal names in generated SystemVerilog (https://github.com/intel/rohd-bridge/pull/44).
• Added intermediateSignalName support to connectPorts and related methods, including same-module loopback and passthrough connections and named-net reuse for fan-out and fan-in (https://github.com/intel/rohd-bridge/pull/45, https://github.com/intel/rohd-bridge/pull/65).
• Fixed a type error in ConnectionExtractor equality checks when compared connections have mismatched types (https://github.com/intel/rohd-bridge/pull/41).

0.2.3

• Added SameModuleConnectionType enum to disambiguate same-module connections involving inOut ports. When connecting two ports on the same module where at least one is inOut and neither is input, a SameModuleConnectionType (loopback or passthrough) must now be provided to gets() or connectPorts() to specify whether the connection should use external-facing or internal-facing ports. (https://github.com/intel/rohd-bridge/pull/39). This change is backwards compatible except for ambiguous scenarios.

0.2.2

• Fixed handling of connections between PairInterfaces that contained subInterfaces, and added checks that exceptPorts are not used in those cases (https://github.com/intel/rohd-bridge/pull/37).
• Fixed a bug where findCommonParent would fail to properly identify a module if both provided arguments were the same module (https://github.com/intel/rohd-bridge/pull/35).

0.2.1

• Fixed a bug where a confusing exception could be thrown if the logger was used but not yet configured (https://github.com/intel/rohd-bridge/pull/32).
• Fixed a bug where if a directory did not exist for a log file, it would crash instead of creating the necessary directory structure (https://github.com/intel/rohd-bridge/pull/32).
• Deprecated logger in BridgeModule.buildAndGenerateRTL in favor of using the default logger (https://github.com/intel/rohd-bridge/pull/32).
• Deprecated enableDebugMesage and fileSink in RohdBridgeLogger (https://github.com/intel/rohd-bridge/pull/32).

0.2.0

• Breaking: PortReference.tieOff and BridgeModule.tieOffInterface now accept value as a named argument instead of a positional argument to support additional arguments (e.g. fill) (https://github.com/intel/rohd-bridge/pull/27).
• Upgraded ConnectionExtractor to support identification of constant tie-offs in addition to port connections and to optionally ignore full interface connections to make some kinds of connection analysis easier (https://github.com/intel/rohd-bridge/pull/27).
• Fixed a bug where calling getsLogic on a sub-array of a port could incorrectly count the number of elements, leading to a confusing error message instead of the expected correct connection (https://github.com/intel/rohd-bridge/pull/28).
• Added parentPortReference to SlicePortReference to allow easier access a port reference one dimension up (https://github.com/intel/rohd-bridge/pull/29).
• Updates to properly support leaving unconnected ports empty in generated SystemVerilog in support of new ROHD features in https://github.com/intel/rohd/pull/638 (https://github.com/intel/rohd-bridge/pull/26).

0.1.4

• Fixed a bug where unpacked array dimensions would be converted to packed dimensions when replicating or pulling up ports (https://github.com/intel/rohd-bridge/pull/24).

0.1.3

• Fixed a limitation where loop-back from an output to an input on the same module was illegal (https://github.com/intel/rohd-bridge/pull/21).

0.1.2

• Improved error messages and exceptions when illegal connections are made in ROHD Bridge, reducing how frequently you get a lower-level ROHD connection error.
• Added the ability to form an internalInterface "later", i.e. if and when it is needed for things like vertical connections with custom port maps (https://github.com/intel/rohd-bridge/pull/11).
• Fixed bugs related to vertical connections (parent/child) of interfaces (https://github.com/intel/rohd-bridge/pull/9).
• Fixed bugs and missing arguments related to exceptPorts in various functions when connecting and creating interfaces (https://github.com/intel/rohd-bridge/pull/17).

0.1.1

• Improved internal APIs related to JSON handling (https://github.com/intel/rohd-bridge/pull/7).

0.1.0

• Initial version of ROHD Bridge.