SlicePortReference class

A PortReference that provides access to sliced or indexed portions of a port.

This class handles complex port access patterns including bit-level slicing and multi-dimensional array indexing. It supports various access patterns while ensuring type safety and proper connection semantics.

Inheritance

Object
PortReference
SlicePortReference

Implementers

SliceInterfacePortReference

Available extensions

TypedPortReferenceConversions

Annotations

@immutable

Constructors

SlicePortReference(BridgeModule module, String portName, {List<int>? dimensionAccess, int? sliceUpperIndex, int? sliceLowerIndex}): Creates a slice port reference with the specified parameters.
SlicePortReference.fromString(BridgeModule module, String portAccessString): Creates a slice port reference from a port access string.
factory

Properties

dimensionAccess ↔ List<int>?: Array dimension and/or bit indices for multi-dimensional array access.
latefinal
direction → PortDirection: The direction of the port (input, output, or inOut).
latefinalinherited
hashCode → int: The hash code for this object.
no setterinherited
hasSlicing → bool: Whether this reference includes slicing.
no setter
module → BridgeModule: The BridgeModule that this reference belongs to.
finalinherited
parentPortReference → PortReference?: The parent PortReference of this SlicePortReference, with slicing or the least significant dimension removed.
no setter
port → Logic: The actual Logic port that this reference points to.
latefinalinherited
portName → String: The name of the port that this reference points to.
finalinherited
portSubset → dynamic: The port subset that this reference represents.
latefinal
portSubsetLogic → Logic: A Logic representation of the port subset.
latefinalinherited
runtimeType → Type: A representation of the runtime type of the object.
no setterinherited
sliceLowerIndex ↔ int?: The lower bound of the slice (inclusive).
latefinal
sliceUpperIndex ↔ int?: The upper bound of the slice (inclusive).
latefinal
subsetDimensions → List<int>?: The array dimensions of the port subset, if applicable.
no setter
subsetElementWidth → int: The bit width of the port subset this reference represents.
no setter
subsetNumUnpackedDimensions → int?: The number of unpacked dimensions in the port subset, if applicable.
no setter
width → int: The bit width of this port reference.
latefinalinherited

Methods

asTyped<PortType extends Logic>() → TypedPortReference<PortType>: Available on PortReference, provided by the TypedPortReferenceConversions extension
Returns this reference as a TypedPortReference when its root port is a PortType.
drivesLogic(Logic other) → void: Drives a Logic other with this port.
override
gets(PortReference other, {SameModuleConnectionType? sameModuleConnectionType, String? intermediateSignalName, bool allowIntermediateSignalNameUniquification = true}) → void: Connects this port to be driven by other.
inherited
getsLogic(Logic other) → void: Connects this port to be driven by a Logic other.
override
getUpdatedSliceIndices(int endIndex, int startIndex) → (int, int): Computes new slice indices when creating a sub-slice of this reference.
noSuchMethod(Invocation invocation) → dynamic: Invoked when a nonexistent method or property is accessed.
inherited
punchDownTo(BridgeModule subModule, {String? newPortName}) → PortReference: Creates a matching port in a submodule and connects them.
inherited
punchUpTo(BridgeModule parentModule, {String? newPortName}) → PortReference: Creates a matching port in the parent module and connects them.
inherited
replicateTo(BridgeModule newModule, PortDirection direction, {String? newPortName}) → PortReference: Creates a new port in the specified module with the given direction.
override
slice(int endIndex, int startIndex) → PortReference: Creates a slice of this port from endIndex down to startIndex.
override
tieOff({dynamic value = 0, bool fill = false}) → void: Ties this port to a constant value.
inherited
toString() → String: A string representation of this object.
override
tryAsTyped<PortType extends Logic>() → TypedPortReference<PortType>?: Available on PortReference, provided by the TypedPortReferenceConversions extension
Returns this reference as a TypedPortReference, or null if its root port is not a PortType.
validate() → void: Validates that this reference resolves to an existing port and subset.
inherited

Operators

operator ==(Object other) → bool: The equality operator.
inherited
operator [](int index) → PortReference: Gets a single bit of this port at the specified index.
inherited

Static Methods

extractPortAccessSliceComponents(String portAccessString) → ({List<int>? dimensionAccess, String portName, int? sliceLowerIndex, int? sliceUpperIndex}): Extracts port access components from a port access string.