rohd
library
Classes
Add
A two-input addition module.
And2Gate
A two-input AND gate.
AndUnary
A unary AND gate.
ARShift
An arithmetic right-shift module.
BusSubset
A Module which gives access to a subset range of signals of the input.
Case
A block of CaseItem s where only the one with a matching CaseItem.value
is executed.
CaseItem
Represents a single case within a Case block.
CaseZ
A special version of Case which can do wildcard matching via z
in
the expression.
Combinational
Represents a block of combinational logic.
Conditional
Represents an some logical assignments or actions that will only happen
under certain conditions.
ConditionalAssign
An assignment that only happens under certain conditions.
ConditionalGroup
Represents a group of Conditional s to be executed.
Const
Represents a Logic that never changes value.
Divide
A two-input divison module.
Else
A conditional block to execute only if condition is satisified.
ElseIf
A conditional block to execute only if condition is satisified.
Equals
A two-input equality comparison module.
ExternalSystemVerilogModule
Represents a Module whose definition exists outside of this framework
in SystemVerilog.
FiniteStateMachine <StateIdentifier >
Simple class for FSM FiniteStateMachine .
FlipFlop
Represents a single flip-flop with no reset.
GreaterThan
A two-input comparison module for greater-than.
GreaterThanOrEqual
A two-input comparison module for greater-than-or-equal-to.
If
Represents a chain of blocks of code to be conditionally executed, like
if
/else if
/else
.
IfBlock
Represents a chain of blocks of code to be conditionally executed, like
if
/else if
/else
.
IndexGate
A two-input bit index gate Module .
Interface <TagType >
Represents a logical interface to a Module .
LessThan
A two-input comparison module for less-than.
LessThanOrEqual
A two-input comparison module for less-than-or-equal-to.
Logic
Represents a logical signal of any width which can change values.
LogicArray
Represents a multi-dimensional array structure of independent Logic s.
LogicStructure
Collects a group of Logic signals into one entity which can be manipulated
in a similar way as an individual Logic .
LogicValue
An immutable 4-value representation of an arbitrary number of bits.
LogicValueChanged
Represents the event of a Logic changing value.
LShift
A logical left-shift module.
Module
Represents a synthesizable hardware entity with clearly defined interface
boundaries.
Modulo
A two-input modulo module.
Multiply
A two-input multiplication module.
Mux
A mux (multiplexer) module.
NotEquals
A two-input inequality comparison module.
NotGate
A gate Module that performs bit-wise inversion.
Or2Gate
A two-input OR gate.
OrUnary
A unary OR gate.
PairInterface
A simplified version of Interface which is intended for a common situation
where two components are communicating with each other and may share some
common inputs.
Pipeline
A simple pipeline, separating arbitrary combinational logic by flop stages.
PipelineStageInfo
Information and accessors associated with a Pipeline stage.
Port
An extension of Logic which performs some additional validation for
inputs and outputs of Module s.
Power
A two-input power module.
ReadyValidPipeline
A pipeline that implements Ready/Valid protocol at each stage.
ReplicationOp
A Replication Operator Module .
RShift
A logical right-shift module.
Sequential
Represents a block of sequential logic.
SimpleClockGenerator
A very simple clock generator. Generates a non-synthesizable SystemVerilog
representation.
Simulator
A functional event-based static simulator for logic behavior.
State <StateIdentifier >
Simple class to initialize each state of the FSM.
Subtract
A two-input subtraction module.
Swizzle
A Module that performs concatenation of signals into one bigger Logic .
SynthBuilder
A generic class which can convert a module into a generated output using
a Synthesizer .
SynthesisResult
An object representing the output of a Synthesizer
Synthesizer
An object capable of converting a module into some new output format
SystemVerilogSynthesizer
A Synthesizer which generates equivalent SystemVerilog as the
given Module .
WaveDumper
A waveform dumper for simulations.
Xor2Gate
A two-input XOR gate.
XorUnary
A unary XOR gate.
Functions
bin (String s )
→ int
Converts a binary String representation to a binary int .
cases (Logic expression , Map conditions , {int ? width , ConditionalType conditionalType = ConditionalType.none , dynamic defaultValue })
→ Logic
Shorthand for a Case inside a Conditional block.
flop (Logic clk , Logic d , {Logic ? en , Logic ? reset , dynamic resetValue })
→ Logic
Constructs a positive edge triggered flip flop on clk
.
mux (Logic control , Logic d1 , Logic d0 )
→ Logic
Performs a multiplexer/ternary operation.
rswizzle (List <Logic > signals )
→ Logic
Performs a concatenation operation on the list of signals, where index 0 of
signals
is the least significant bit(s).
swizzle (List <Logic > signals )
→ Logic
Performs a concatenation operation on the list of signals, where index 0 of
signals
is the most significant bit(s).